library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity MDR is
    port(Clk,LD_MDR: in  bit;
         MDR_in:    in  unsigned(15 downto 0);
         MDR_out:    out unsigned(15 downto 0));
end entity MDR;

architecture build of MDR is
    begin
        process(LD_MDR,MDR_in,Clk)
            begin
                if Clk = '1' and Clk'event then
                    if LD_MDR = '1' then
                        MDR_out <= MDR_in;
                    end if;
                end if;
            end process;
    end build;
